13728818899
13728818899
| organization | Standard series | Scope of application |
|---|---|---|
| JEDEC | JESD series | The most widely used semiconductor device testing method, reliability testing, and failure mechanism in the world |
| IEC | 60747, 60748, etc | General specification for semiconductor discrete devices and integrated circuits |
| AEC | AEC-Q100 (IC), Q101 (discrete), Q200 (passive) | Automotive electronic component certification (high reliability) |
| MIL | MIL-STD-883 (microelectronic devices), 750 (semiconductor devices) | Military/aerospace grade components |
| ISO | ISO 26262 (Functional Safety) | Functional Safety of Automotive Chips |
| China | GB/T 4589.1 (General Specification for Semiconductor Devices), GJB 597B (Microelectronic Devices) | Civilian and military chips |
Note: JEDEC JESD22 and JESD47 are the most commonly used standards for reliability testing of consumer and industrial chips.
| test project | JEDEC standard | IEC standards | explanation |
|---|---|---|---|
| Input/output leakage current | JESD78 (included in the latch up effect test) | IEC 60747-1 | Measure the leakage level of pins |
| Power supply current (static/dynamic) | JESD24（MOSFET） | IEC 60748-2 (Digital IC) | Evaluate power consumption |
| Output voltage/logic level (VOH, VOL, VIH, VIL) | JESD8 (Logic Level) | IEC 60748-1 | Verify logical compatibility |
| Propagation delay (tpd) | JESD65 (timing parameters) | – | Critical path testing |
| Fan out capability (load driving capability) | – | IEC 60748-1 | Output current capability |
| Frequency/clock stability | JESD12 (oscillator test) | – | High speed chips (PLL/DLL) |
Testing principle: Apply a test pattern and compare the output with the expected simulation value.
Common methods: Scan Chain, Built in Self Test (BIST), Boundary Scan (JTAG, IEEE 1149.1).
Relevant standards:
IEEE 1149.1 (JTAG Boundary Scan Test Standard)
IEEE 1500 (Embedded Chip Testing Standard)
There is no independent JEDEC functional testing standard, but the testing method is mentioned in JESD12 (Digital IC Testing Method).
This is the most important part of chip testing, used to evaluate the failure rate under long-term use.
| test item | JEDEC standard | AEC-Q100 corresponds to (automotive) | Corresponding to MIL-STD-883 | Example of conditions |
|---|---|---|---|---|
| High temperature working life (HTOL) | JESD22-A108 | Section 3 | Method 1005 | 125 ° C/150 ° C, 1000 hours |
| High temperature and high humidity bias (H3TRB/THB) | JESD22-A101 | Section 4 | – | 85 ° C/85% RH, 1000 hours, bias voltage |
| Temperature and humidity without bias (TH) | JESD22-A100 | – | – | 85 ° C/85% RH, 1000 hours, no bias voltage |
| High Acceleration Temperature Humidity Stress Test (HAST) | JESD22-A110 (biased)/A118 (unbiased) | Section 4 | – | 130 ° C/85% RH, 96 hours |
| Thermal Cycle (TC) | JESD22-A104 | Section 5 | Method 1010 | -65 ° C~150 ° C, 500/1000 cycles |
| Thermal Shock (TS) | JESD22-A106 | – | Method 1011 | Gas liquid or liquid-liquid, larger Δ T |
| High temperature storage (HTS) | JESD22-A103 | – | Method 1008 | 150 ° C/175 ° C, 1000 hours |
| Low temperature storage (LTS) | JESD22-A119 | – | – | -40 ° C/-55 ° C, 1000 hours |
| Intermittent Operating Life (IOL, Power Cycle) | JESD22-A105 | Section 7 | Method 1015.9 (partial) | Simulate thermal stress during power on/off operation |
| Early Failure Rate (ELFR) | JESD92 (Sampling Method) | Section 8 | – | Batch screening, 124hr, 125 ° C dynamic |
| Electrostatic Discharge (ESD) |
JESD22-A114（HBM） JESD22-A115（CDM） JESD22-A116（MM） |
Section 9 | Method 3015 (HBM) | HBM：2kV/4kV； CDM：500V/1000V |
| Latch up effect | JESD78 (E/F level) | Section 11 | – | ± 100mA or 1.5 x Vmax |
| Welding heat resistance (WSH) | JESD22-A113 (Preprocessing) | – | – | Simulated reflow soldering, up to 260 ° C |
| Tin ball cutting/pushing force | JESD22-B117 / JEP159 | – | – | Evaluate the mechanical strength of solder joints/packaging |
| test item | standard | explanation |
|---|---|---|
| Ultrasound scanning (C-SAM) | JESD22-B126 (Acoustic Microscope) | Detect delamination, voids, and cracks |
| X-ray inspection | JESD22-B128 (Guidelines for X-ray Imaging Work) | Observe wire bonding, voids, and solder beads |
| Scanning Electron Microscope (SEM) | JESD22-B109 (Metal Layer Failure Localization) | Observe surface morphology and subtle defects |
| Bonding strength (lead/solder) | JESD22-B116 (wire bonding strength), JESD22-B115 (gold aluminum compound detection) | Destructive or non-destructive tensile force |
| Mold plastic Tg/CTE | JESD22-B107 (Thermal Mechanical Analysis TMA) | Glass transition temperature, coefficient of expansion |
| Moisture Sensitivity Level (MSL) | JESD22-A113 (Preprocessed J-STD-020) | Determine the moisture-proof requirements before reflow soldering |
AEC-Q100 has added stricter temperature levels (Grade 0: -40 ° C~150 ° C), long-term reliability (such as higher temperature cycles), and statistical yield monitoring for zero defect requirements based on JEDEC.
Key documents:
AEC-Q100 Rev-H (Chip Stress Test Certification)
AEC-Q006 (Power Device with Copper Leads)
ZVEI (German Electrical and Electronics Association) method (for power cycle life assessment)
MIL-STD-883K (Test Methods for Microelectronic Devices): covers environmental, mechanical, electrical testing, and durability (such as 1000 hours of high temperature life).
MIL-PRF-38535 (General Specification for Integrated Circuits): defines the QML/QPL certification system.
China: GJB 597B (General Specification for Semiconductor Integrated Circuits), GJB 548B (Test Methods for Microelectronic Devices, Equivalent to MIL-STD-883).
| technology | Common methods/standards | purpose |
|---|---|---|
| Luminescent microscope (EMMI) | – | Locate the leakage path |
| OBIRCH (Laser Beam Induced Resistance Change) | JESD24 (partially related) | Detecting short/open circuits in metal wires |
| Focused Ion Beam (FIB) | – | Circuit modification and cross-sectional observation |
| Liquid Chemical Open Cap (Decap) | JESD22-B111 (copper wire cover opening) | Expose the surface of the chip |
| Substrate removal/backside analysis | JESD22-B100 (back polished) | – |
| Chip type | Characteristic standards | Typical tests |
|---|---|---|
| Memory chip (DRAM/Flash) | JESD47 (Reliability Qualification), JESD218 (SSD Durability Test Specification) | Durability testing (P/E cycle), data retention (high-temperature baking), interference testing (read/write disturbance) |
| Power devices (MOSFET/IGBT) | JESD24 (power MOSFET electrical characteristics), JESD22-A113 (intensified temperature and humidity bias) | Breakdown voltage, on resistance, avalanche withstand (EAS), short-circuit withstand, IOL power cycling |
| Logic/microprocessor | JESD12 (Digital IC Testing Methods), IEEE 1500 (Embedded Core Testing) | Function vector, scan testing, timing testing |
| Analog/Mixed Signal | JESD10 (ADC Test Guide) | DC accuracy, linearity, signal-to-noise ratio, total harmonic distortion |
| Radio Frequency Chip (RFID) | JESD22-A101 (with particular attention to s-parameter drift under temperature and humidity) | Gain, noise figure, standing wave ratio IP3、EVM |
| Optoelectronic chips (optical transceiver, LED) | JESD22-A115 (CDM is particularly strict), IES LM-80 (LED luminous flux maintenance) | Optical power, spectrum, eye diagram (high-speed) |
| Test Name | content | reference standard |
|---|---|---|
| Online Parameter Monitoring (WAT) | Test the Vt, Ids, and breakdown voltage on the test key | Enterprise standards can refer to JEP121 (Statistical Process Control) |
| Wafer probing (CP) | Complete basic functional testing, DC parameter testing, and partial speed testing on the wafer | There is no unified standard, but the testing method must comply with JEDEC parameter definitions |
| Defect detection (optical/electron beam) | Surface particles, scratches, bridging | SEMI standards (such as SEMI P22) |
| Standard Number | name | Corresponding to international standards |
|---|---|---|
| GB/T 4589.1-2006 | Semiconductor devices - Part 1: General principles | IEC 60747-1 |
| GB/T 16464-1996 | General specification for semiconductor device integrated circuits | – |
| GB/T 4937 series | Mechanical and climatic testing methods for semiconductor devices | JESD22 series (similar) |
| GJB 597B-2015 | General Specification for Semiconductor Integrated Circuits (Military Standard) | MIL-PRF-38535 |
| GJB 548B-2005 | Test methods and procedures for microelectronic devices | MIL-STD-883 |
| GB/T 35000-2018 | Integrated Circuit Electromagnetic Emission Testing Method (1kHz~1GHz) | IEC 61967 |
Wafer testing (CP) → packaging → finished product testing (FT, single station) → reliability sampling (ORT, by batch).
CP/FT testing: 100% electrical parameter and functional testing (not mandatory by JEDEC, according to product specifications).
Reliability batch acceptance: Conduct periodic sampling life and environmental tests according to JEDEC JESD47 or AEC-Q100.
JESD47 defines that at least three batches of samples should be taken per batch/quarter to complete all assessment items such as HTOL, THB/HAST, TC, ESD, etc.
Production line monitoring: According to JEP122 (early failure) and JEP131 (life test sampling table).
Each batch of packaging is pre processed according to JESD22-A113 (simulating upstream SMT), followed by TC, HTS, H3TRB, etc.
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Phone: 13728818899
Email: ata@certata.com
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Phone: 0755-82828582
Mobile phone: 13728818899
Email: ata@certata.com
